ASIC and FPGA Verification: A Guide to Component Modeling
Richard Munden
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
類別:
年:
2004
版本:
First Edition
出版商:
Morgan Kaufmann
語言:
english
頁數:
337
ISBN 10:
0125105819
ISBN 13:
9780125105811
系列:
Systems on Silicon
文件:
PDF, 3.14 MB
IPFS:
,
english, 2004